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The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XL device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx® Virtex®, Spartan®-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint.
The XC9500XL architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life.
Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times.
Key Features
Optimized for high-performance 3.3V systems
5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
Pb-free available for all packages
Lower power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS FastFLASH technology
Advanced system features
In-system programmable
Superior pin-locking and routability with FastCONNECT II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with individual product-term allocation
Local clock inversion with three global and one product-term clocks
Individual output enable per output pin with local inversion
Input hysteresis on all user and boundary-scan pin inputs
Bus-hold circuitry on all user pin inputs
Supports hot-plugging capability
Full IEEE Std 1149.1 boundary-scan (JTAG) support on all devices
Four pin-compatible device densities
36 to 288 macrocells, with 800 to 6400 usable gates
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
10,000 program/erase cycles endurance rating
20 year data retention
Pin-compatible with 5V core XC9500 family in common package footprints
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